1. Field of the Invention
The present invention relates to a solid state image pickup apparatus which integrates an array of photoelectric conversion elements arranged on a semiconductor substrate, and a scanning circuit for extracting optical information from these photoelectric conversion elements.
2. Related Background Art
A solid state image pickup apparatus converts spatial two-dimensional optical information to an electrical signal in a time series, and generally has an photoelectric conversion function and a scanning function.
In order to reduce the image bandwidth and to obtain an image of high resolution and low flicker, the standard television system employs a so-called interlacing system which scans horizontal scanning lines alternately and forms a picture (one frame) from two fields.
Conventionally, an interlacing system is proposed which selects horizontal scanning lines two by two in a different combination in each field (Unexamined Published Patent Application No. 155010/1977). Also, a circuit structure which embodies this system has been proposed (Unexamined Published Patent Application No. 29517/1979). These prior arts will now be described with reference to the drawings.
FIGS. 4A and 4B show a first circuit structure for the prior art interlaced scanning and the operational timing of the structure. In FIG. 4A, a horizontal scanning circuit 1 produces scanning pulses to open and close horizontal switching MOS field effect transistors (hereinafter refers to MOSTs) 2. Reference numeral 3 denotes a vertical scanning circuit. Reference numerals 4-1, 4-2, 4-3 and 4-4 denote interlacing selector switches. These switches each may include a MOS transistor. These switches are connected at one end (for example, source) to the corresponding stage output Oy1, Oy2, . . . OYM of a unit circuit included in the vertical scanning circuit 3 and at the other end (for example, drain) to lines Lv (Lv1, Lv2, Lv3, Lv4, Lv5, . . . Lv(2M-1), Lv(2M), Lv(2M+1) to each of which the gates of corresponding vertical switching MOSTs 5 are connected in common. One picture (hereinafter referred to as one frame) is composed of two fields (a first field and a second field). Each pair of switches 4-1, 4-2 are opened and closed by a first field pulse F1 applied to a terminal 6 to form a first field while each pair of switches 4-3, 4-4 are opened and closed by a second field pulse F2 applied to a terminal 7 to form a second field. Photodiodes PD include corresponding sources of MOSTs 5. Vertical signal output lines Ly (Ly1, Ly2, Ly3 . . . ) each have sources of corresponding MOSTs 5 connected thereto. A horizontal signal output line Lx has drains of MOSTs 2 connected thereto in common.
In this prior art, as shown in the timing chart of FIG. 4B, vertical scanning circuit 3 is clocked by clock pulses to sequentially output scanning pulses Vy1, Vy2, . . . VyM, which are shifted by a predetermined timing time (1H interval) in a field relative to the circuit stage outputs Oy1, Oy2, . . . OyM sequentially.
A horizontal scanning circuit 1 outputs scanning pulses Vx1, Vx2, Vx3, Vx4, . . . sequentially to the respective stage outputs Ox1, Ox2, Ox3, Ox4, . . . of a unit circuit included therein.
Two vertical and horizontal scanning pulses designate a position (X, Y), and the optical signal charges stored in the photodiode PD at that position during a field interval is read through the corresponding vertical and horizontal switches 5 and 2 onto the output line Lx. Such reading is performed sequentially at other positions.
The operation of this prior art will be described in more detail with respect to the timing chart of FIG. 4B.
In a first field, a first field pulse F1 becomes "1" which is applied via the terminal 6 to the gates of switches 4-1, 4-2 to thereby render switches 4-1, 4-2 conductive. Therefore the respective stage outputs Oy1, Oy2, Oy3, . . . OyM of vertical scanning circuit 3 are connected to corresponding pairs of scanning pulse application lines Lv1, Lv2; Lv3, Lv4; . . . ; (Lv(2M-1), Lv(2M)).
In a second field, a second field pulse F2 becomes "1" which is applied via the terminal 7 to the gates of switches 4-3, 4-4 to thereby render switches 4-3, 4-4 conductive (switches 4-1, 4-2 are non-conductive), Therefore, the respective stage outputs Oy1, Oy2, Oy3, . . . OyM of the vertical scanning circuit 3 are connected to corresponding pairs of scanning pulse application lines Lv2, Lv3; Lv4, Lv5; . . . ; Lv(2M), Lv(2M+1)
Consequently, rows are selected two by two in a different combination in each field to thereby obtain two-line pixel synthesized signals S1, S2.
FIG. 5 shows another prior art. In FIG. 5A, interlacing selector switches 4 (4-1, 4-2, 4-3, 4-4) have gates connected to the corresponding stage outputs Oy1, Oy2, . . . OyM of a unit circuit included in vertical scanning circuit 3. The switches 4 are sequentially opened and closed by vertical scanning pulses Vy1, Vy2, . . . VyM during each 1H. Terminals 6 and 7 receive first and second field pulses F1' and F2', respectively. Switches 4-1, 4-2 receive at one end (for example, source) first field pulse, and are connected at the other end (for example, drain) to vertical scanning pulse application line Lv. Switches 4-3, 4-4 receive at one end (for example, source) a second field pulse and are connected at the other end (for example, drain) to vertical scanning pulse application line Lv. In this example, when reading of a selected row is completed, the voltage stored on the scanning pulse application line Lv for the completed row must be discharged to the "0" level.
Therefore, as shown in the timing chart of FIG. 5B, the voltages of field pulses F1', F2' must be dropped to the "0" level a predetermined interval Tf before the "1" level interval of scanning pulses Vy1, Vy2 . . . VyM ends. The interval Tf is only required to be sufficient for the voltage remaining on the scanning pulse application line to discharge from the "1" level to the "0" level via switch 4, and is only required to be set to a value within a horizontal blanking period (approximately 10 .mu.s) provided for each horizontal interval. The relationship in timing between horizontal and vertical scanning pulses is similar to that of FIG. 4.
In the above two prior arts, there is a small number of components of the circuit to embody the interlaced scanning system. A pitch per vertical scanning circuit stage is reduced, so that the pitch at which pixels are arranged is reduced to thereby improve the resolution.
In the prior art shown in FIG. 4, the respective stage outputs Oy1-OyM of the unit circuit included in vertical scanning circuit drive vertical scanning pulse application lines Lv1-Lv(2M+1) to which a plurality of MOST gates are connected in common via selector switch MOSTs. Thus, the respective output stages of the unit circuit in the vertical scanning circuit must have the ability to drive the vertical scanning pulse application lines sufficiently. The drive ability is required to increase with the area of the circuit, so that the area where the vertical scanning circuit 3 is laid out increases. Such is the problem.
In the prior art shown in FIG. 5, an output pulse from the unit circuit included in the vertical scanning circuit 3 turns on four selector switches simultaneously, so that a conductive path is formed between the first field pulse application terminal F1' and the second field pulse application terminal F2'. Therefore, the operational timing of FIG. 5B cannot well drive vertical scanning pulse application lines.